1. Field of the Invention
The invention relates generally to the field of circuits for processing information in binary form, and more specifically to circuits for adding a plurality of numbers in word form having a selected number of binary digits, or bits. The circuit will find greatest utility in applications that require the addition of a large number of binary words, each comprising a smaller number of bits; that is, where the number of binary words, M, to be added exceeds the number of bits N in each word.
2. Description of the Prior Art
Adder circuits typically add pairs of numbers, in the form of digital words. However, if a particular application requires more than two words to be added together, such additions normally are performed on an iterative basis, with each word being added to a previous sum. Adders are usually used in data processing equipment that includes a clocking signal, and each addition is performed in synchronism therewith. Accordingly, the number of pulses of the clock signal that is required to add the words together approaches the number of words to be added; specifically, the number of clock pulses required is one less than the number of words that are being summed. It can be seen that if a large number of words are to be summed, a large amount of time, measured in clock pulses, may be spent in performing the addition.